Heterogeneous computing platforms (HCP) are computer systems made with combinations of different processing element types. The iconic Central Processing Unit (CPU) processing element type is used for the vast majority of computations by computers in the world, but interest in HCPs is growing. This growth is linked to the increased accessibility to programmers of formerly fringe processing element types.
Graphics Processing Units (GPU), which comprise one such processing element type, have become more accessible to programmers for more than exclusively graphics-related tasks. Likewise, Field Programmable Gate Arrays (FPGA), which comprise another such element type, are devices with programmable digital logic hardware that can be reconfigured in-place.
FPGAs have been used for years in routers and niche markets, yet concurrently with GPUs, have become more accessible to programmers for other computing tasks. As a consequence of this increased accessibility, HCPs have become strategically important for datacenters, which can use combinations of different processing element types for higher computational efficiency and energy savings. The recent acquisition by Intel Corporation of one of the two largest FPGA manufacturers, Altera Corporation, has clearly marked this trend towards HCPs. Intel has subsequently announced the upcoming availability of an HCP comprised of an Intel CPU with an Altera FPGA in the same package to its customers.
The trend toward HCPs is worldwide. Data and processing centers of tech giants have announced plans to use HCPs with FPGAs to save energy. However, designing systems with FPGAs is not straightforward as special skills are required that are rarely possessed by mainstream software developers.
One area where HCPs would be highly applicable is in the field of genomics. Specifically, the field is concerned with an archetypical series of steps flowing from raw data to fully analyzed genomes that we call here the Genome Processing Pipeline (GPP). Demand for improvements in the GPP is on the rise. With the advent of high throughput sequencing, genomics has entered a new era where massive quantities of data are produced (2-40 ExaBytes/year in 2025 are expected). The sequencing of one human genome generates of the order of 100GB of compressed raw data. These data are small sequences (also called reads), which are randomly located in the genome, with high redundancy (typically 30x-50x). Even when focused only on the exome (the protein coding part of the chromosomal
DNA), sequencing still generates 10GB of raw data per genome. Processing these data in a timely fashion is currently the limiting step in the genome sequencing process. For example, it takes around 700 minutes to process a single exome sequencing data set on a standard 8 core AMD processor and around 7 days on one 32-core computer for a whole genome.
While acceleration is part of the objective, a very important effect of exploiting FPGAs resides in the power consumption reduction. They can consume much less power than standard CPUs for the same calculation (for instance Microsoft reduced it by 50% for their Bing page ranking engine). In a world of energy saving issues and for a sustainable environment, achieving the objectives of this project will significantly reduce the operating costs of large scale genome analysis applications and enable a wide variety of hospitals and institutions to acquire and run massive data analytics.

More in detail, the quantitative objectives of the project are the following:

1. Execution of the whole genome processing pipeline in less than an hour. It will specifically have to accelerate the following algorithms:

    • Alignment: Alignment of the sequences onto a reference genome to find their most probable location
    • Variant calling: To find where the genome shows inter-individual or intra-individual variability

2. A 50% reduction of power consumption for typical execution of the GPP, compared to the existing implementation.

Investigation into at least three different target platforms will occur. Some additional targets will optionally be investigated, as their availability and feasibility are less certain. Considering the pace in this industry, other new devices are likely to be put on the market during the time frame of this project. The architecture to be developed will facilitate addressing these targets in the future, thanks to its modularity. The following is a list of anticipated targets to be investigated in this project: (1) Standard PCIe boards, where the FPGA is seen as a PCIe device, (2) Multi-FPGA PCIe board, exploiting up to 6 FPGAs to take maximum advantage of hardware acceleration, (3) Intel-Altera new device (Intel has recently announced the upcoming availability of a new CPU-FPGA chip in a single package).