# TASYMO

The objective of this project was to create a new reconfigurable and scalable architecture for the interpolation of an incremental signal, that can process more than 15 Gb/s of data. The main target market is the dimensional metrology, with possible applications in other industries.

This project has studied the possibilities offered by the latest generation of FPGA, but also the study of solutions with little material resources and low cost such as DSP-based microcontrollers.

# State of the art

An interpolator is traditionally made of an electrical interface (TTL or 1Vpp) connected to the optical rule through differential SIN and COS signals. These signals are sampled by an analog to digital converter with N bits. Then, the discretized signals are converted into an angular value [2π, 0] by means of the ARCTAN (arctangent) mathematical function. This angle represents the position of the measuring head between two consecutive main units of the optical rule.

The interpolation factor (FIP) is described as the number of measurements (steps) obtained in this cycle.

As this quantity of measurements comes from the converter, it depends directly on its frequency and resolution (number of bits).

The FIP is therefore firstly, directly linked to the characteristics of A/D converter and secondly, to the movement speed of the measuring head. The higher the speed, the shorter the cycle will become and therefore will decrease the interpolation factor.

# Innovation

In the scope of this project, an innovative and flexible solution able to meet much higher constraints is proposed:

- To increase the moving speed of the measuring head from 2.5 m/s to 8m/s
- To obtain a 1nm resolution over the entire speed range
- To make the FIP independent from the A/D converter and get a multiplication factor of 512x up to 20000x.
- A scalable and reprogrammable multi-protocol system

# Results

Different solutions have been developed based on two complementary technologies: FPGA and DSP. Each of them targets different technological industrial domains.

The architecture illustrated below shows some details of the prototype board based on a FPGA.

This solution met all the planned objectives, i.e. 1nm of resolution at a speed of 8m/s independently of A/D converter.

The DSP solution is already in the process of industrialization by the industry partner.