The DEMESYS project aims at developing a methodology for the design and verification of complete systems combining an FPGA, an embedded processors and a PC.
The realization of complete systems involving hardware processing on an FPGA, an embedded processor and a PC is not an easy task, especially due to the communication between these different elements. Too many projects only partially test the entire system, performing only few unit tests on the separate components.
In this context, the DEMESYS project seeks to provide guidelines and methodologies for the development of such systems in order to minimize development time and the risk of having an unreliable system. We are mainly interested in the Zync SoC at first.
The idea behind this project is to validate the different parts of the system individually, and then validate the interactions between all these parts. To achieve that, individual components are replaced by mock parts backed up by a simulator.
As a first step in the project we are targeting the CPU-FPGA co-simulation, using Qemu for the software part and Questasim for the FPGA side.