Cache Memory on FPGA for external DDR with Multiple Agents
November 2016 - December 2016
  • FPGA
Hardware-oriented Efficient Information Processing

The CMF project goal was to develop a cache memory on FPGA in order to improve the performances of systems requiring access to an external memory (DDR). The design has been realized based on standard cache principles as well as with the ability to arbiter between multiple access interfaces. Therefore, more than one module can access the same external memory (that will be shared).

The description language is VHDL, and the result could be integrated within the TURNUS tool. Its aim is to automatically generate a hardware description (in verilog) of a program written in CAL (CAL Actor Language). This actor-based language does not offer a good management of shared memory among actors. The last developments of TURNUS are going into this direction, but no arbiter is yet available.

The cache memory is supplied as an IP and can be exploited by any project. It is generic in data size and address bus size. The memory is set-associative, with block size and number of sets being also generic. As previously mentioned, it can be attached to many modules, thanks to its arbiter.

The results of CMF should be useful for the community, and the cache memory could be used in further REDS institute projects, as accessing an external memory is often an issue in any FPGA project.